Flash memory is in increasing usage as storage memory in solid-state storage systems. Each flash memory cell can be erased, through removal of charge from a floating gate of the cell, and programmed, through addition of charge to the floating gate of the cell. To read a value from the cell, one bit for single level cell flash, and two or more bits for multilevel cell flash, a read voltage is applied to a control gate of the cell, and the cell either conducts or does not conduct, depending on whether the read voltage exceeds or does not exceed the threshold voltage for the cell. Threshold voltage (whether programmed or not) can drift over time, from charge loss (or gain), aging of circuitry, and other causes. Some flash memories have adjustable read voltage(s), to compensate for threshold voltage drift. One standard technique for storage systems is to apply a default read voltage until errors become unacceptable, then try another read voltage in attempt to recover data, and afterwards reverting to the default read voltage for subsequent accesses. With aging flash memory or long-term storage of data, this standard technique results in multiple retries and longer read times, which the user observes as longer latency for data reads. Therefore, there is a need in the art for a solution which overcomes the drawbacks described above.